The present invention relates to a waveform generating apparatus for generating a test signal having a desired waveform and a semiconductor device testing apparatus using this waveform testing apparatus.
A waveform generating apparatus for generating a test signal having a desired waveform is used, for example, in a semiconductor device testing apparatus for testing a semiconductor device. FIG. 26 shows an example of a conventional semiconductor device testing apparatus (hereinafter referred to as IC tester) for testing a semiconductor integrated circuit (including a large-scale integrated circuit (LSI); hereinafter referred to as IC) which is a typical example of a semiconductor device. This IC tester comprises, roughly speaking, a pattern generator PG, a timing generator 20, a waveform shaping circuit FC, a driver DR, a level comparator LCP, and a logical comparator CP.
A main controller (not shown) mainly controls the pattern generator PG and the timing generator 20. This main controller is generally constituted by a computer system, and controls the pattern generator PG, the timing generator 20, and the like in accordance with a test program created by a user.
First, before a testing for an IC is started, various kinds of data are set by the main controller. After those various kinds of data have been set, the testing for an IC is started. By applying a test start instruction or command from the main controller to the pattern generator PG, the pattern generator PG starts to generate a pattern. The pattern generator PG supplies test pattern data (logical data) PAT to the waveform shaping circuit FC as well as supplies a test period signal PS (Period-Start) and a timing signal TS to the timing generator 20 in accordance with the control of the main controller.
In order for the timing generator 20 to add a predetermined amount of delay to the period signal PS supplied from the pattern generator PG, the timing generator 20 has a delay data memory 11 provided therein in which a plurality of timing (phase) delay data TD differing from one another have been previously stored. The timing generator 20 delays the period signal PS by an amount of delay corresponding to a timing delay data stored in an address of the delay data memory 11 specified by the supplied timing signal TS, and outputs the delayed period signal PS. This delayed period signal PS is supplied to the waveform shaping circuit FC as a timing pulse TPO, and also, is supplied to the logical comparator CP as a comparison clock pulse (strobe pulse) STRB.
The waveform shaping circuit FC generates a test pattern signal FCO having a desired real waveform on the basis of a test pattern data PAT supplied from the pattern generator PG and a timing pulse TPO supplied from the timing generator 20. This test pattern signal FCO is amplified by the driver DR, and then is applied, as an input signal Si, to an IC under test (hereinafter referred to as DUT) 19.
Here, in case that the DUT 19 is a memory IC (an IC the memory portion of which is the principal part), or in case of testing the memory portion of a system LSI (a large-scale integrated circuit in which the logic portion and the memory portion are present in mixture on one chip), or the like, the test pattern signal Si is stored in a predetermined memory cell of the DUT 19, and the stored content is read out in a read cycle carried out later. On the contrary, in case that the DUT 19 is a logic IC (an IC the logic portion of which is the principal part), or in case of testing the logic portion of a system LSI, or the like, the result of a logical operation of the test pattern signal Si is outputted from the DUT 19 as a response signal So.
A response signal So read out from the DUT 19 is compared by the level comparator LCP with a reference voltage supplied from a comparison reference voltage source (not shown) to determine whether or not the response signal has a predetermined logical level, that is, a voltage SH of logical H (logical high) or a voltage SL of logical L (logical low). The response signal determined to have the predetermined logical level is sent, as a logical signal SH or SL, to the logical comparator CP where the response signal is compared with an expected value pattern signal EP outputted from the pattern generator PG to determine whether or not the DUT 19 has outputted a normal response signal.
If the response signal (SH or SL) does not coincide with the expected value pattern signal EP, a memory cell having an address of the DUT 19 from which the response signal was read out is determined to be defective (failure) in case that the memory portion of the DUT 19 is being tested, or in case that the DUT 19 is a memory IC, or the like, and a failure signal FAIL indicating that fact is generated from the logical comparator CP. Usually, when this failure signal FAIL is generated, a write operation of a failure data (in general, a signal of logical xe2x80x9c1xe2x80x9d) being applied to a data input terminal of a failure analysis memory (not shown) is enabled, and the failure data is stored in the failure analysis memory at an address thereof specified by an address signal being supplied to the failure analysis memory at that time. Generally, the same address signal as that has been applied to the DUT 19 is applied to the failure analysis memory, and hence the failure data is stored in an address of the failure analysis memory that is the same as that of the DUT 19.
On the contrary, if the response signal coincides with the expected value pattern signal EP, a memory cell having an address of the DUT 19 from which the response signal was read out is determined to be normal, and a pass signal PASS indicating that fact is generated. Usually, this pass signal PASS is not stored in the failure analysis memory.
At a time point that the testing has been completed, the failure data stored in the failure analysis memory are read out therefrom, and then, for example, whether or not a relief or repair of the failure memory cells of the tested DUT 19 is possible is determined.
On the other hand, in case that the DUT 19 is a logic IC, or in case of testing the logic portion of a system LSI, or the like, when the response signal (SH or SL) does not accord with the expected value pattern signal EP, the test pattern signal having brought about that disaccord between the response signal and the expected value pattern signal, an address at which the test pattern signal has been generated, logical data outputted from a pin of the DUT 19 having outputted the response signal which does not accord with the expected value pattern signal EP, the expected value pattern data compared with the logical data at that time, and the like are stored in the failure analysis memory. Those data are utilized, after the completion of the test, in analyzing a cause of the failure occurrence mechanism, evaluating the tested LSI, or the like.
The timing generator 20 generates timing signals such as timing pulses TPO for defining respectively a rise timing and a fall timing of the waveform of the test pattern signal to be applied to the DUT 19, a strobe pulse (clock pulse) STRB for defining a timing of a logical comparison between the response signal and the expected value pattern signal EP in the logical comparator CP, and the like.
Timings and periods for generating such timing signals are described in a test program created by the user, and the IC tester is constructed such that a test pattern signal is applied to the DUT 19 with an operating period and at a timing intended by the user to operate the DUT 19 so that whether the DUT 19 operates in normal condition or not can be tested.
Since the waveform generating apparatus mainly comprises the timing generator 20 and the waveform shaping circuit FC, several specific examples of the timing generator 20 will be first described.
FIG. 27 is a block diagram showing a first specific example of the timing generator 20, and FIG. 28 is a timing chart for explaining its operation. This first timing generator 20 comprises a delay data memory (register) 11 in which a plurality of timing delay data TD are previously stored as mentioned above, a delay counter 12 that is an n-bit parallel down-counter (decrement-counter), a NAND circuit 13, an AND circuit 14, a variable delay circuit 15, and a data conversion table 15a. 
As to a case that the reference clock period T is set to 10 ns (T=10 ns), the test period Tt is set to 100 ns that is ten times of the reference clock period T (Tt=10xc3x97T=100 ns), and a timing delay data 3xc3x97T+(xc2xd)xc3x97T=35 ns that is one of the plurality of timing delay data TD previously stored in the delay data memory 11 is designated by a timing signal TS outputted from the pattern generator PG, the operation of the timing generator 20 for outputting a timing pulse TPO will be discussed.
To the clock terminal CK of the delay counter 12 is externally supplied the reference clock REFCK having the reference clock period T=10 ns shown in FIG. 28A, and a test period signal (period start signal) PS having the test period Tt=100 ns shown in FIG. 28B is supplied to the load terminal Ld of the delay counter 12. On the other hand, a delay coefficient xe2x80x9c3xe2x80x9d representing the integer in the timing delay data TD (3xc3x97T+(xc2xd)xc3x97T) is supplied to the data input terminal di of the delay counter 12 from the delay data memory 11, and also a delay coefficient xe2x80x9cxc2xdxe2x80x9d representing the fraction lower than the decimal point in the timing delay data TD is supplied to the data conversion table (memory) 15a from the delay data memory 11. The integer delay coefficient xe2x80x9c3xe2x80x9d supplied to the delay counter 12 is preset therein.
The delay counter 12 decrements by one, when the test period signal PS is applied to the load terminal Ld thereof, its internal data xe2x80x9c3xe2x80x9d each time the reference clock REFCK is supplied thereto, and outputs binary data representing decimal numbers of xe2x80x9c2xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d to the n-bit output terminals in the sequence of xe2x80x9c2xe2x80x9dxe2x86x92xe2x80x9c1xe2x80x9dxe2x86x92xe2x80x9c0xe2x80x9d. The output terminals of the delay counter 12 are connected to the input terminals of the NAND circuit 13. Accordingly, when the NAND circuit 13 detects that all of the outputs from the n-bit output terminals of the delay counter 12 have become zeros, the NAND circuit 13 outputs to its output terminal an analog delay start signal ADS (analog delay start) which becomes logical H level only during the time interval T after it has been delayed by the time duration of 3T, as shown in FIG. 28C.
This analog delay start signal ADS is supplied to one of the input terminals of the AND circuit 14, thereby to enable the AND circuit 14. Since the reference clock REFCK is supplied to the other of the input terminals of the AND circuit 14, it outputs therefrom an analog delay start signal ADSxe2x80x2 shown in FIG. 28D and having a time width (time duration) of xc2xd of the period T of the reference clock REFCK, and the analog delay start signal ADSxe2x80x2 is inputted to the variable delay circuit 15.
The fraction delay coefficient xe2x80x9cxc2xdxe2x80x9d supplied to the data conversion table 15a from the delay data memory 11 is converted into a control signal (a select signal) by the data conversion table 15a, and the control signal is inputted to the control terminal S of the variable delay circuit 15. The variable delay circuit 15 is controlled by the control signal to delay the inputted analog delay start signal ADSxe2x80x2 by a time interval of (xc2xd)xc3x97T corresponding to the delay coefficient xe2x80x9cxc2xdxe2x80x9d, thereby to generate a timing pulse TPO, as shown in FIG. 28E. Thus, from the first timing generator 20a is outputted the timing pulse TPO delayed by the time duration equivalent to the timing delay data TD=3xc3x97T+(xc2xd)xc3x97T stored in the delay data memory 11 and designated by the timing signal TS.
FIG. 29A shows a specific example of the variable delay circuit 15, and FIG. 29B shows an example of the data conversion table 15a. The variable delay circuit 15 is provided with three multiplexers MUX0, MUX1 and MUX2 connected in cascade between its input terminal IN and its output terminal OUT. An output signal ADSxe2x80x2 from the AND circuit 14 is supplied to the input terminal IN of the variable delay circuit 15, and select signals S0, S1 and S2 from the data conversion table 15a are supplied to control terminals S of these multiplexers MUX0, MUX1 and MUX2, respectively. As can be easily understood from FIG. 29B, the data conversion table 15a applies, when the fraction delay coefficient is xe2x80x9cxc2xdxe2x80x9d (corresponds to the delay time of T/2), the select signals S0=0, S1=0 and S2=1 to the control terminals S of the multiplexers MUX0, MUX1 and MUX2, respectively. Each of the multiplexers MUX0, MUX1 and MUX2 is constructed such that it selects its input terminal A when a select signal is xe2x80x9c0xe2x80x9d (zero) and selects its input terminal B when a select signal is xe2x80x9c1xe2x80x9d (one). Accordingly, in this case, only the multiplexer MUX2 selects the input terminal B, and delays the output signal ADSxe2x80x2 from the AND circuit 14 through its delay circuit (the delay time of which is set to T/2). As a result, the output signal ADSxe2x80x2 from the AND circuit 14 is delayed by only the time interval of T/2 and is outputted from its output terminal OUT as a timing pulse TPO.
FIG. 30 is a block diagram showing a second specific example of the timing generator 20, and FIG. 31 is a timing chart for explaining its operation. Similarly to the above first specific example, this second timing generator 20 comprises a delay data memory (register) 11 in which a plurality of timing delay data TD are previously stored, a delay counter 12 that is an n-bit parallel down-counter (decrement-counter), a NAND circuit 13, an AND circuit 14, a variable delay circuit 15, and a data conversion table 15a, and in addition thereto, it further comprises an operation circuit 16 for adding an output signal of the delay data memory 11 and a fraction data FD shorter than the reference clock period T (not inclusive of T), and a delay circuit 17 for adjusting (delaying) the phase of the reference clock REFCK such that the output signal of the NAND circuit 13 can surely coincide with the reference clock REFCK in the AND circuit 14. The second timing generator 20 is configured such that the output signal of the delay data memory 11 and the fraction data FD shorter than the reference clock period T are summed in the operation circuit 16, and an integer delay coefficient Sa representing an integer delay time equal to or longer than the reference clock period T (inclusive of T) in the summed result is supplied to the data input terminal di of the delay counter 12 and a fraction delay coefficient Sb representing a fraction delay time shorter than the reference clock period T is supplied to the data conversion table 15a. In other words, the second timing generator 20 is different from the first timing generator shown in FIG. 28 in the point that the second timing generator 20 is constructed such that it can also cope with even a case in which the test period Tt includes a fraction lower than the decimal point, namely, a decimal place, in addition to an integer.
As to a case that the reference clock period T is set to 10 ns (T=10 ns), the test period Tt is set to 5xc3x97T+(xc2xe)xc3x97T ns (Tt=57.5 ns), and a timing delay data 3xc3x97T+(xc2xd)xc3x97T=35 ns that is one of the plurality of timing delay data TD previously stored in the delay data memory 11 is designated by a timing signal TS outputted from the pattern generator PG, the operation of the timing generator 20 for outputting a timing pulse TPO will be discussed.
To the clock terminal CK of the delay counter 12 is externally supplied the reference clock REFCK having the reference clock period T=10 ns shown in FIG. 31A, and a test period signal (period start signal) PS having the test period Tt=57.5 ns shown in FIG. 31B is supplied to the load terminal Ld of the delay counter 12. On the other hand, the timing delay data TD (3xc3x97T+(xc2xd)xc3x97T) shown in FIG. 31C from the delay data memory 11 and the fraction data FD shown in FIG. 31D representing a fraction time duration shorter than the reference clock period T are summed in the operation circuit 16, and an integer delay coefficient Sa shown in FIG. 31E representing an integer delay time equal to or longer than the reference clock period T in the summed result is supplied to the data input terminal di of the delay counter 12 and also a fraction delay coefficient Sb shown in FIG. 31F representing a fraction delay time shorter than the reference clock period T is supplied to the data conversion table (memory) 15a. The integer delay coefficient Sa supplied to the delay counter 12 is preset therein.
Since the test period Tt includes the fraction lower than the decimal point, the start cycle T0 is set to have its period of 5T corresponding to the integer part of the test period Tt, thereby to make the fraction part shorter than the reference clock period T zero. Consequently, the fraction data (Period-fractional data) FDxe2x88x920 in the start cycle T0 is set to zero, and the remaining fraction time duration (xc2xe)T in the test period Tt is carried over to the next second cycle T1.
The operation circuit 16 sums the timing delay data TD=(3+xc2xd)T given from the delay data memory 11 and the fraction data FDxe2x88x920=0 (T), and supplies an integer delay coefficient xe2x80x9c3xe2x80x9d (Sa=3) representing the delay time 3T of the integer part in the summed result (3+xc2xd)T to the data input terminal di of the delay counter 12, and also a fraction delay coefficient xc2xd (Sb=xc2xd) representing the delay time (xc2xd)T of the fraction part in the summed result (3+xc2xd)T to the data conversion table 15a. 
The delay counter 12 decrements by one, when a rise edge of the start test period signal PSxe2x88x920 is applied to the load terminal Ld thereof, its internal data xe2x80x9c3xe2x80x9d each time the reference clock REFCK is supplied thereto, and outputs binary data representing decimal numbers of xe2x80x9c2xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d to the n-bit output terminals in the sequence of xe2x80x9c2xe2x80x9dxe2x86x92xe2x80x9c1xe2x80x9dxe2x86x92xe2x80x9c0xe2x80x9d. The output terminals of the delay counter 12 are connected to the input terminals of the NAND circuit 13. Accordingly, when the NAND circuit 13 detects that all of the outputs from the n-bit output terminals of the delay counter 12 have become zeros, the NAND circuit 13 outputs to its output terminal an analog delay start signal ADS which becomes logical H level only during the time interval T after it has been delayed by the time duration of 3T from the rise edge of the start test period signal PSxe2x88x920, as shown in FIG. 31G.
This analog delay start signal ADS is supplied to one of the input terminals of the AND circuit 14, thereby to enable the AND circuit 14. Since the reference clock REFCK whose phase has been adjusted by the delay circuit 17 is supplied to the other of the input terminals of the AND circuit 14, it outputs therefrom an analog delay start signal ADSxe2x80x2 shown in FIG. 31H and having a time width (time duration) of xc2xd of the period T of the reference clock REFCK, and the analog delay start signal ADSxe2x80x2 is inputted to the variable delay circuit 15.
The fraction delay coefficient xe2x80x9cxc2xdxe2x80x9d supplied to the data conversion table 15a from the operation circuit 16 is converted into a select signal by the data conversion table 15a, and the select signal is inputted to the control terminal S of the variable delay circuit 15. Since the variable delay circuit 15 and the data conversion table 15a shown in FIG. 29 can also be used in this case as the variable delay circuit 15 and the data conversion table 15a, the detailed explanation thereof will be omitted. The variable delay circuit 15 delays the inputted analog delay start signal ADSxe2x80x2 by a time interval of (xc2xd)T corresponding to the fraction delay coefficient xe2x80x9cxc2xdxe2x80x9d, thereby to generate a timing pulse TPOxe2x88x920 shown in FIG. 31I. In this manner, the timing pulse TPOxe2x88x920 is generated at the time point that a time duration of (3+xc2xd)T has elapsed from the rise edge of the start test period signal PSxe2x88x920. As a result, in the start cycle T0, the timing pulse TPOxe2x88x920 is generated, which is delayed by a time duration equivalent to the timing delay data TD=(3+xc2xd)T stored in the delay data memory 11 and designated by the timing signal TS.
Though the next second cycle T1 would have a time duration of (5+xc2xe)T+(xc2xe)T=(6+xc2xd)T which is the sum of the fraction time duration (xc2xe)T carried over from the start cycle T0 and the second test period Tt, the fraction time duration (xc2xd)T is carried over to the next third cycle T2 so that the second cycle T1 can be set to have its period of 6T which is the integer time duration. As a result, in the second cycle T1, the fraction data FD becomes (xc2xe)T.
Like the case of the start cycle T0, the operation circuit 16 sums the timing delay data TD=(3+xc2xd)T given from the delay data memory 11 and the fraction data FDxe2x88x921=(xc2xe)T, and supplies an integer delay coefficient xe2x80x9c4xe2x80x9d (Sa=4) representing the delay time 4T of the integer part in the summed result (4+xc2xc)T to the data input terminal di of the delay counter 12 and a fraction delay coefficient xc2xc(Sb=xc2xc) representing the delay time (xc2xc)T of the fraction part in the summed result (4+xc2xc)T to the data conversion table 15a, respectively.
The delay counter 12 decrements by one, when a rise edge of the second test period signal PSxe2x88x921 is applied to the load terminal Ld thereof, its internal data xe2x80x9c4xe2x80x9d each time the reference clock REFCK is supplied thereto, and outputs binary data representing decimal numbers of xe2x80x9c3xe2x80x9d, xe2x80x9c2xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d to the n-bit output terminals in the sequence of xe2x80x9c3xe2x80x9dxe2x86x92xe2x80x9c2xe2x80x9dxe2x86x92xe2x80x9c1xe2x80x9dxe2x86x92xe2x80x9c0xe2x80x9d. Consequently, the delay counter 12 outputs to its output terminal an analog delay start signal ADS which becomes logical H level only during the time interval T after it has been delayed by the time duration of 4T from the rise edge of the second test period signal PSxe2x88x921, as shown in FIG. 31G.
This analog delay start signal ADS is supplied to one of the input terminals of the AND circuit 14, thereby to enable the AND circuit 14. Since the reference clock REFCK whose phase has been adjusted by the delay circuit 17 is supplied to the other of the input terminals of the AND circuit 14, it outputs therefrom an analog delay start signal ADSxe2x80x2 shown in FIG. 31H and having a time width (time duration) of xc2xd of the period T of the reference clock REFCK, and the analog delay start signal ADSxe2x80x2 is inputted to the variable delay circuit 15.
As is apparent from the data conversion table 15a shown in FIG. 29B, select signals corresponding to the fraction coefficient xc2xcare S0=0, S1=1 and S2=0. Accordingly, only the multiplexer MUX1 selects its input terminal B. As a result, the variable delay circuit 15 delays the inputted analog delay start signal ADSxe2x80x2 by a time duration of (xc2xc)xc3x97T corresponding to the fraction delay coefficient xe2x80x9cxc2xcxe2x80x9d, thereby to generate a timing pulse TPOxe2x88x921 shown in FIG. 31I. This timing pulse TPOxe2x88x921 is generated at the time point that the time duration of (4+xc2xc)T has elapsed from the rise edge of the second test period signal PSxe2x88x921. However, since the rise edge of the second test period signal PSxe2x88x921 has entered into the start test period side by the time duration of (xc2xe)T, the timing pulse TPOxe2x88x921 is generated at the time point that the time duration of (4+xc2xc)Txe2x88x92(xc2xe)T=(3+xc2xd)T has elapsed from the starting point of the second test period. Thus, in the second cycle T1, the timing pulse TPOxe2x88x921 is generated, which is also delayed by the time duration equivalent to the timing delay data TD=(3+xc2xd)T stored in the delay data memory 11 and designated by the timing signal TS.
Though the next third cycle T2 would have a time duration of (5+3/4)T+(xc2xd)T=(6+xc2xc)T which is the sum of the fraction time duration (xc2xd)T carried over from the second cycle T1 and the test period Tt, the fraction time duration (xc2xc)T is carried over to the next fourth cycle T3 so that the third cycle T2 can be set to have its period of 6T which is the integer time duration. As a result, in the third cycle T2, the fraction data FD becomes (xc2xd)T.
Like the case of the second cycle T1, the operation circuit 16 sums the timing delay data TD=(3+xc2xd)T given from the delay data memory 11 and the fraction data FDxe2x88x922=(xc2xd)T. The result of the addition becomes (3+xc2xd+xc2xd)T=4T which has no fraction. Consequently, only an integer delay coefficient xe2x80x9c4xe2x80x9d (Sa=4) representing the delay time 4T of the integer part in the summed result 4T is given to the data input terminal di of the delay counter 12.
Since the operation of the delay counter 12 is the same as that of the delay counter in the second cycle, the explanation thereof will be omitted. The delay counter 12 outputs to its output terminal an analog delay start signal ADS which becomes logical H level only during the time interval T after it has been delayed by the time duration of 4T from the rise edge of the third test period signal PSxe2x88x922, as shown in FIG. 31G. This analog delay start signal ADS is supplied to one of the input terminals of the AND circuit 14. Accordingly, the AND circuit 14 outputs an analog delay start signal ADSxe2x80x2 shown in FIG. 31H, which is in turn inputted to the variable delay circuit 15.
Since the variable delay circuit 15 outputs the inputted analog delay start signal ADSxe2x80x2 without giving any delay thereto, a timing pulse TPOxe2x88x922 shown in FIG. 31I is generated. This timing pulse TPOxe2x88x922 is generated at the time point that the time duration of 4Txe2x88x92(xc2xd)T=(3+xc2xd)T has elapsed from the starting point of the third test period because the rise edge of the third test period signal PSxe2x88x922 has entered into the second test period side by the time duration of (xc2xd)T. Thus, in the third cycle T2, the timing pulse TPOxe2x88x922 is generated, which is also delayed by the time duration equivalent to the timing delay data TD=(3+xc2xd)T stored in the delay data memory 11 and designated by the timing signal TS.
After that, similar operations to those described above will be repeated for each of the periods in the fourth cycle T3 and the subsequent cycles thereto.
FIG. 32 is a block diagram showing a third specific example of the timing generator 20, and FIG. 33 is a timing chart for explaining its operation. This third timing generator 20 comprises two timing generators 20 each of which is the same construction as that of the above-mentioned second specific example shown in FIG. 30, and is constructed such that the two timing generators 20A and 20B are operated in interleave mode (alternately operated in regular sequence), and timing pulses TPOA and TPOB alternately outputted from variable delay circuits 15A and 15B of the respective timing generators 20A and 20B are summed in an OR circuit 21. Each of the two timing generators 20A and 20B has the same construction as that of the timing generator of the above-mentioned second specific example, and hence portions and elements of the first timing generator 20A corresponding to those of the timing generator of the second specific example will be shown by the same reference characters with xe2x80x9cAxe2x80x9d affixed thereto, and also, portions and elements of the second timing generator 20B corresponding to those of the timing generator of the second specific example will be shown by the same reference characters with xe2x80x9cBxe2x80x9d affixed thereto. The explanations of those portions and elements will be omitted unless it is necessary.
Similarly to the above-mentioned second specific example, as to a case that the reference clock period T is set to 10 ns (T=10 ns), the test period Tt is set to 5xc3x97T+(xc2xe)xc3x97T ns (Tt=57.5 ns), and a timing delay data 3xc3x97T+(xc2xd)xc3x97T=35 ns that is one of the plurality of timing delay data TD previously stored in each of the delay data memories 11A and 11B of the respective timing generators 20A and 20B is designated by a timing signal TS outputted from the pattern generator PG, the operations of both the timing generators 20A and 20B will be briefly discussed.
A reference clock REFCK having the reference clock period T=10 ns shown in FIG. 33A is externally supplied to each of the clock terminals CK of the delay counters 12A and 12B (12B is not shown) of the respective timing generators 20A and 20B, and the same address signal TS is supplied to the delay data memories 11A and 11B of the respective timing generators 20A and 20B. However, since these timing generators 20A and 20B are operated in interleave mode, the test period signals (period start signals) PSA and PSB to be supplied to the load terminals Ld of the respective delay counters respectively are given every two test periods (every a time duration of 2xc3x97Tt=(11+xc2xd)T), as shown in FIGS. 33B and 33G. In addition, the fraction data FDA and FDB each being shorter than the reference clock period T to be inputted to the operation circuits 16A and 16B respectively are also given every two test periods, as shown in FIGS. 33C and 33H.
In this specific example, since the interleave operation is performed, the first timing generator 20A is operated in odd periods such as the start cycle T0, the third cycle T2, the fifth cycle T4, . . . , and the second timing generator 20B is operated in even periods such as the second cycle T1, the fourth cycle T3, the sixth cycle T5, . . . Accordingly, the test period signals PSA are sequentially supplied to the load terminal Ld of the delay counter 12A at the starting point of each of the odd periods T0, T2, T4, . . . , and the test period signals PSB are sequentially supplied to the load terminal Ld of the delay counter 12B (not shown) at the starting point of each of the even periods T1, T3, T5, . . . Likewise, the fraction data FDA (0T, (xc2xd)T, . . . ) of the odd periods T0, T2, T4, . . . are sequentially inputted to the operation circuit 16A at the starting point of each of the odd periods, and the fraction data FDB ((xc2xe)T, (xc2xc)T, . . . ) of the even periods T1, T3, T5, . . . are sequentially supplied to the operation circuit 16B at the starting point of each of the even periods.
As a result, the first timing generator 20A generates, as shown in FIG. 33F, timing pulses TPOA in only odd periods at the time point that a time duration (3T+(xc2xd)T) corresponding to the timing delay data TD has elapsed from the starting point of each of the odd periods, and the second timing generator 20B generates, as shown in FIG. 33K, timing pulses TPOB in only even periods at the time point that a time duration (3T+(xc2xd)T) corresponding to the timing delay data TD has elapsed from the starting point of each of the even periods. Accordingly, the timing pulses TTPO of the entire timing generator 20 outputted from the OR circuit 21 become timing pulses each of which is delayed only by a time duration (3T+(xc2xd)T) corresponding to the timing delay data TD from the starting point of each of the test periods, as shown in FIG. 33L. Consequently, if both of the timing generators 20A and 20B are operated at the same speed as that of the timing generator in the second specific example shown in FIG. 30, timing pulses can be generated from the timing generators 20A and 20B at double the speed of generation of timing pulses from the timing generator in the second specific example. In addition, if the number of interleaves (the number of timing generators to be sequentially switched to operate) is increased, timing pulses can be generated at a speed multiplied by the number of interleaves.
Next, several specific examples of the waveform generating apparatus will be described, which includes a waveform shaping circuit FC for generating a test pattern signal FCO having a desired real waveform on the basis of test pattern data PAT supplied from the pattern generator PG and timing pulses TPO supplied from the timing generator 20.
In one test period Tt, a waveform in which data (waveforms) at both sides of a data (waveform) having logical value xe2x80x9c1xe2x80x9d in a logical signal are xe2x80x9c0sxe2x80x9d without fail or a waveform in which data (waveforms) at both sides of a data (waveform) having logical value xe2x80x9c0xe2x80x9d in a logical signal are xe2x80x9c1sxe2x80x9d without fail, is called an SBC waveform (surrounded by complement waveform). FIG. 34 is a block diagram showing a first specific example of the waveform generating apparatus which is capable of generating a test pattern signal having this SBC waveform, or a test pattern signal having an NRZ (nonreturn to zero) waveform or an RZ (return to zero) waveform, and FIG. 35 is a timing chart for explaining the operation of the first specific example. A generated test pattern signal FCO is applied to a DUT 19.
As shown in FIG. 34, the waveform generating apparatus of this first specific example comprises three of first, second and third timing generators TGA, TGB and TGC, a memory circuit 41 to which a waveform mode selecting signal WM for specifying either one of an SBC waveform, an NRZ waveform or an RZ waveform and a test pattern data PAT from the pattern generator PG are inputted, and a waveform shaping circuit FC for generating an SBC waveform, an NRZ waveform or an RZ waveform on the basis of timing pulses supplied from these timing generators TGA, TGB and TGC respectively and a pattern data supplied from the memory circuit 41.
Though the timing generators TGA, TGB and TGC are illustrated with only a variable delay circuit VD shown in their blocks, each of the timing generators may have the same circuit configuration as that of the timing generator 20 of the second specific example shown in FIG. 30. Accordingly, as mentioned above, the timing generators TGA, TGB and TGC generate timing pulses TPOA, TPOB and TPOC respectively on the basis of a test period signal PS and a timing signal TS supplied from the pattern generator PG as well as a fraction data FD shorter than the reference clock period T. Further, each of the variable delay circuits VD corresponds to the variable delay circuit 15 in the timing generator 20 of the second specific example.
The waveform shaping circuit FC comprises six of first to sixth AND gates AND1-AND6, six of first to sixth variable delay circuits 33-38 for delaying output signals from these AND gates AND1-AND6 respectively, a first OR gate 39 for executing a logical OR operation of the first, third and fifth delay circuits 33, 35 and 37, a second OR gate 40 for executing a logical OR operation of the second, fourth and sixth delay circuits 34, 36 and 38, and an S-R (set-reset) flip-flop 26 to the set terminal of which is applied an output signal of the first OR gate 39 and the reset terminal of which is applied an output signal of the second OR gate 40.
In order to make it possible to use a timing pulse outputted from each of the timing generators as either of a set pulse Ss and a reset pulse Sr to the S-R flip-flop 26, two AND gates have been provided at the output side of each of the timing generators. A timing pulse TPOA from the first timing generator TGA is supplied in common to one input terminals of the first and second AND gates AND1 and AND2, a timing pulse TPOB from the second timing generator TGB is supplied in common to one input terminals of the third and fourth AND gates AND3 and AND4, and a timing pulse TPOC from the third timing generator TGC is supplied in common to one input terminals of the fifth and sixth AND gates AND5 and AND6. Further, a timing pulse for setting (or a set timing pulse) outputted from each of the timing generators is supplied to the first OR gate 39, and a timing pulse for resetting (or a reset timing pulse) outputted from each of the timing generators is supplied to the second OR gate 40.
The memory circuit 41 is provided with a gate control table 41a which outputs control data for controlling the AND gates AND1-AND6 in their enable states or disable states. When a waveform mode selecting signal WM and a test pattern data PAT are inputted to the memory circuit 41, the memory circuit 41 supplies control data D1-D6 corresponding to a waveform specified by this waveform mode selecting signal WM to the other input terminals of the corresponding AND gates AND1-AND6, respectively. In the illustrated example, D1 is supplied to the AND gate AND1, D2 to the AND gate AND2, D3 to the AND gate AND3, D4 to the AND gate AND4, D5 to the AND gate AND5, and D6 to the AND gate AND6.
FIG. 36 shows an example of the gate control table 41a. In case that the logical value of the test pattern data PAT is xe2x80x9c0xe2x80x9d, the control data shown in left sides of slash lines in FIG. 36 are outputted in accordance with a specified waveform, and in case that the logical value of the test pattern data PAT is xe2x80x9c1xe2x80x9d, the control data shown in right sides of the slash lines are outputted in accordance with a specified waveform. The outputted control data are supplied to the other input terminals of the corresponding AND gates AND1-AND6, respectively. In the gate control table 41a shown in FIG. 36, the control data xe2x80x9cONxe2x80x9d represents an enable state of each of the AND gates, and the control data xe2x80x9cOFFxe2x80x9d represents a disable state of each of the AND gates.
First of all, in case that a waveform mode selecting signal WM specifies an SBC waveform, and the logical value of a test pattern data PAT is in order of xe2x80x9c0xe2x80x9dxe2x86x92xe2x80x9c1xe2x80x9dxe2x86x92xe2x80x9c0xe2x80x9d. . . as shown in FIG. 35C, in the start cycle T0, the logical value of the test pattern data PAT is xe2x80x9c0xe2x80x9d. As a result, from the gate control table 41a shown in FIG. 36, D1 is ON, D2 is OFF, D3 is OFF, D4 is ON, D5 is ON and D6 is OFF. Accordingly, the first, fourth and fifth AND gates AND1, AND4 and AND5 become enable states respectively so that the timing pulses TPOA, TPOB and TPOC can pass through these AND gates, and the timing pulses TPOA and TPOC can be used as set pulses Ss as shown in FIG. 35H, and the timing pulse TPOB can be used as a reset pulse Sr as shown in FIG. 35H. In the second cycle T1, the logical value of the test pattern data PAT is xe2x80x9c1xe2x80x9d, and hence D1 is OFF, D2 is ON, D3 is ON, D4 is OFF, D5 is OFF and D6 is ON. As a result, the second, third and sixth AND gates AND2, AND3 and AND6 become enable states respectively so that the timing pulses TPOA, TPOB and TPOC can pass through these AND gates, and only the timing pulse TPOB can be used as a set pulse Ss as shown in FIG. 35G, and the timing pulses TPOA and TPOC can be used as reset pulses Sr as shown in FIG. 35H. Since the operation in the third cycle is the same as that in the start cycle, the explanation thereof will be omitted. Further, in the timing chart shown in FIG. 35, in case that one period of the reference clock REFCK is set to T, the test period Tt is set to {6+(xc2xd)}T. Accordingly, the time interval of the start cycle T0 is set to 6T, the time interval of the second cycle T1 is set to 7T, the time interval of the third cycle T2 is set to 6T, . . .
As a result, from the S-R flip-flop 26 is outputted a test pattern signal FCO having the SBC waveform shown in FIG. 35I. As can easily be understood from this SBC waveform, in each test period Tt, the data of logical value xe2x80x9c0xe2x80x9d in the test pattern data PAT is shaped into a waveform of logical value xe2x80x9c0xe2x80x9d having an effective time duration Tv, which has, at the both sides thereof, a waveform of logical xe2x80x9c1xe2x80x9d having a time duration T0 and a waveform of logical xe2x80x9c1xe2x80x9d having a time duration T3. On the other hand, the data of logical value xe2x80x9c1xe2x80x9d in the test pattern data PAT is shaped into a waveform of logical value xe2x80x9c1xe2x80x9d having an effective time duration Tv, which has, at the both side thereof, a waveform of logical xe2x80x9c0xe2x80x9d having a duration time T0 and a waveform of logical xe2x80x9c0xe2x80x9d having a duration time T3.
Next, in case that a waveform mode selecting signal WM specifies an RZ waveform, two of the timing generators are used. Since the second and third timing generators TGB and TGC are used in this example, the timing pulses TPOA outputted from the first timing generator TGA must be made unavailable. Therefore, as shown in the gate control table 41a in FIG. 36, the control data D1 and D2 are always made OFF so that the first and second AND gates AND1 and AND2 can always be made disable state.
Next, in case that a waveform mode selecting signal WM specifies an NRZ waveform, only one of the timing generators is used, and the first timing generator TGA is used in this example. Accordingly, the timing pulses TPOB and TPOC outputted respectively from the second and third timing generators TGB and TGC must be made unavailable. Thus, as shown in the gate control table 41a in FIG. 36, the control data D3-D6 are always made OFF so that the third to the sixth AND gates AND3-AND6 can always be made disable state.
FIG. 37 is a block diagram showing a second specific example of the waveform generating apparatus which is capable of generating a test pattern signal having an SBC waveform, an NRZ waveform or an RZ waveform. This second specific example comprises two waveform generating apparatuses each of which has the same construction as that of the above-mentioned first specific example shown in FIG. 34, and is constructed such that the two waveform generating apparatuses are operated in interleave mode (alternately operated in regular sequence) so that timing pulses can be alternately outputted from both the waveform generating apparatuses, thereby to generate timing pulses at double the speed of generation of timing pulses from one waveform generating apparatus. Since each of the two waveform generating apparatuses has the same construction as that of the waveform generating apparatus of the above-mentioned first specific example, portions and elements of the first waveform generating apparatus corresponding to those of the waveform generating apparatus of the first specific example will be shown by the same reference characters, and portions and elements of the second waveform generating apparatus corresponding to those of the waveform generating apparatus of the first specific example will be shown by the same reference characters with a prime (xe2x80x2) affixed thereto. In addition, with respect to a test pattern data PAT, a test period signal PS and a timing signal TS supplied from the pattern generator PG, and a fraction data FD shorter than the reference clock period T, signals and data supplied to the first waveform generating apparatus will be shown by the same reference characters with a sign xe2x80x9c-Axe2x80x9d affixed thereto, and signals and data supplied to the second waveform generating apparatus will be shown by the same reference characters with a sign xe2x80x9c-Bxe2x80x9d affixed thereto. Since the operation of the waveform generating apparatus of the second specific example can easily be understood from the operation of the aforementioned waveform generating apparatus of the first specific example and the description of the interleave operation with reference to FIG. 33, the explanation thereof will be omitted.
Here, referring to the waveform generating apparatus of the first specific example shown in FIG. 34 again, the timing pulses TPOA, TPOB and TPOC respectively outputted from the timing generators TGA, TGB and TGC must be supplied to the set terminal and the reset terminal of the S-R flip-flop 26 in phase with one another. For this reason, the variable delay circuits 33-38 are inserted into the output sides of the AND gates AND1-AND6, respectively, to adjust delay times (propagation delay times) of these timing pulses TPOA, TPOB and TPOC in their respective propagation paths (that is, to make skew adjustments) so that the timing pulses can reach the set terminal and the reset terminal of the S-R flip-flop 26 in phase with one another.
Now, the sum of propagation delay times (Txe2x88x92Tpd) of a timing pulse propagating through the propagation path La including the analogously configured variable delay circuit 33 for skew adjustment and the variable delay circuit VD of the timing generator TGA fluctuates depending upon changes in temperature and voltage, and amounts of the fluctuations can be expressed by following equations.
xcex94T1=(Txe2x88x92Tpd)xc3x97(temperature fluctuation coefficient of Tpd)xc3x97(xc2x1temperature changing width)xe2x80x83xe2x80x83(1)
xcex94T2=(Txe2x88x92Tpd)xc3x97(temperature fluctuation coefficient of Tpd)xc3x97(xc2x1voltage changing width)xe2x80x83xe2x80x83(2)
For example, if it is assumed that Txe2x88x92Tpd is equal to 10 ns, the temperature fluctuation coefficient is 0.3%/xc2x0 C., and the environmental temperature of the IC tester is 25xc2x15xc2x0 C., the following result is obtained.                               Δ          ⁢                      xe2x80x83                    ⁢          T1                =                  xe2x80x83                ⁢                  10          xc3x97          0.3          xc3x97                      10                          -              2                                xc3x97                      (                          ±              5                        )                    ⁢                      xe2x80x83                    ⁢                      (            ns            )                                                  =                  xe2x80x83                ⁢                                            ±                              xe2x80x83                            ⁢              0.15                        ⁢                          xe2x80x83                        ⁢                          (              ns              )                                =                                    ±              150                        ⁢                          xe2x80x83                        ⁢            ps                              
A similar result is obtained for a timing pulse propagating through another propagation path.
In the waveform generating apparatus of the first specific example shown in FIG. 34 and the waveform generating apparatus of the second specific example shown in FIG. 37, the variable delay circuit of each timing generator is connected in cascade with the corresponding variable delay circuit for skew adjustment. Therefore, there is a drawback that the total propagation delay time (Txe2x88x92Tpd) becomes large, and hence the amount of temperature fluctuation xcex94T1 and the amount of voltage fluctuation xcex94T2 in the propagation delay time have large values, which results in degradation of the timing accuracy.
In addition, due to the limitations in performance of input/output buffers of an LSI constructed as the waveform generating apparatus, a high frequency reference clock cannot be inputted to the waveform generating apparatus from the outside. For this reason, as a procedure for improving the operation speed, there has been used a procedure called interleave operation (multiplexed operation) in which a plurality of timing generators are prepared, and these timing generators are sequentially switched to alternately operate them, as shown in FIGS. 32 and 37. However, if the interleave operation is adopted, almost all of the modules (elements) including the timing generators must be prepared as many as the number of interleaves, and hence the scale of the hardware is increased to about one multiplied by the number of interleaves. Particularly, in the waveform generating apparatus adopting the interleave operation shown in FIG. 37, six timing generators are required although the number of interleaves is two (2).
Moreover, the variable delay circuit 15 or VD of each of the timing generators utilizes gate delays of a plurality of gate elements connected in cascade, as shown in FIG. 29A, and hence a considerable process steps are needed to create a data conversion table for converting logical delay times into control (select) signals as shown in FIG. 29B. For the waveform generating apparatus shown in FIG. 34, since three variable delay circuits VD are used, three data conversion tables must be created. For the waveform generating apparatus adopting the interleave operation shown in FIG. 37, since six variable delay circuits VD are used, six data conversion tables must be created. If the number of interleaves is further increased to make the operation speed higher, the number of variable delay circuits to be used is also increased. Accordingly, there is a drawback that process steps for creating data conversion tables are much increased.
Furthermore, as shown in FIG. 37, the set pulse Ss supplied to the set terminal and the reset pulse Sr supplied to the reset terminal of the SR flip-flop 26 are obtained as the results of logical OR operations of the timing pulses propagating through six propagation paths, respectively. As a result, there is a problem that a slight unevenness is liable to occur in corrections of the delay times (slew adjustments) of the respective propagation paths, and hence the timing accuracy is further deteriorated.
It is an object of the present invention to provide a waveform generating apparatus which can solve the aforementioned problems occurring in the prior art and a semiconductor device testing apparatus having this waveform generating apparatus therein.
It is another object of the present invention to provide a waveform generating apparatus which can improve the timing accuracy and in which the scale of the hardware can be simplified while its superficial interchangeability with the prior art hardware is maintained, and a semiconductor device testing apparatus having this waveform generating apparatus therein.
In order to accomplish the aforesaid objects, in a first aspect of the present invention, there is provided a waveform generating apparatus comprising: delay data selecting means selecting, out of a plurality of delay data, at least one delay data for generating at least one set pulse and at least one delay data for generating at least one reset pulse in accordance with test logical data and waveform mode information externally supplied thereto; skew data storage means for set pulse and for reset pulse, said skew data storage means storing therein skew adjusting delay data for a propagation path of a delay data for set pulse and for a propagation path of a delay data for reset pulse, respectively; operation means for set pulse and for reset pulse, said operation means performing an operation of the set pulse delay data, the skew adjusting delay data for set pulse and a fraction data in each test cycle externally supplied thereto and an operation of the reset pulse delay data, the skew adjusting delay data for reset pulse and a fraction data in each test cycle externally supplied thereto, respectively, and outputting an integer delay data and a fraction delay data for set pulse from the result of the operation and an integer delay data and a fraction delay data for reset pulse from the result of the operation, respectively; delay means for set pulse and for reset pulse, said delay means outputting at least one set pulse generating effective flag for causing a timing of a test period to delay by a delay time corresponding to the integer delay data and at least one reset pulse generating effective flag for causing a timing of a test period to delay by a delay time corresponding to the integer delay data, respectively, as well as outputting fraction delay data related to these set pulse generating effective flag and reset pulse generating effective flag, respectively; variable delay means for set pulse and for reset pulse, to which the set pulse generating effective flag and the reset pulse generating effective flag are inputted respectively, said variable delay means delaying the effective flags on the basis of the related fraction delay data, respectively; and waveform outputting means outputting a waveform which is set by a set pulse supplied from said set pulse variable delay means and reset by a reset pulse supplied from said reset pulse variable delay means, for each test period.
In a preferred embodiment, the waveform generating apparatus further includes a delay data memory for storing therein said plurality of delay data, and said delay data selecting means comprises: a select data memory for generating data selecting information in accordance with test logical data and waveform mode information externally supplied thereto; and a multiplexer for selecting, out of the plurality of delay data supplied from said delay data memory, said at least one delay data for generating at least one set pulse and said at least one delay data for generating at least one reset pulse, by the data selecting information supplied from said select data memory.
In addition, it is preferable that said select data memory has data selecting information stored therein corresponding to waveform mode information, test logical data of current test cycle and previous test cycle, and the set pulse effective flag and the reset pulse effective flags.
The aforesaid delay data selecting means may comprise: a select data memory in which data selecting information corresponding to the waveform mode information and test logical data of current test cycle and previous test cycle is stored; and a multiplexer which is capable of selecting, out of the data selecting information inputted thereto from said select data memory and the plurality of delay data inputted thereto from a delay data memory, said at least one set pulse generating delay data and said at least one reset pulse generating delay data, and the set pulse effective flag and the reset pulse effective flag in the first half or the second half of a period signal.
The aforesaid variable delay means comprise: set pulse and reset pulse data conversion means each outputting a delay control signal corresponding to the fraction delay data; and set pulse and reset pulse variable delay circuits for delaying, on the basis of the delay control signals outputted from said data conversion means, the set pulse generating effective flag and the reset pulse generating effective flag inputted thereto, respectively.
It is preferable that the data selecting information stored in said select data memory is set such that when the test logical data is a sequence of the same logical values such as xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, xe2x80x9c1xe2x80x9d in adjacent test cycles, the set pulse or the reset pulse is inhibited from being consecutively inputted to said waveform outputting means.
The aforesaid set pulse delay means and the aforesaid reset pulse delay means may perform operations of the set pulse integer delay data and an output of a counter for counting a clock and of the reset pulse integer delay data and an output of a counter for counting a clock, thereby to generate set pulse and reset pulse counter data coincidence expected values, respectively, and detect coincidences between said coincidence expected values and the output of said counter and output the set pulse generating effective flag and the reset pulse generating effective flag as well as the set pulse fraction delay data and the reset pulse fraction delay data related to these effective flags, respectively.
It is preferable that control means is provided for inhibiting an input data from being loaded in said set pulse delay means and said reset pulse delay means in case that an open flag for inhibiting a pulse from being outputted is given to a delay data supplied to said multiplexer from said delay data memory, and also, in case that a set/reset pulse effective flag is not present in data selecting information supplied to said multiplexer from said select data memory.
In a second aspect of the present invention, there is provided a semiconductor device testing apparatus for testing a semiconductor device comprising: delay data selecting means selecting, out of a plurality of delay data, at least one delay data for generating at least one set pulse and at least one delay data for generating at least one reset pulse in accordance with test logical data and waveform mode information externally supplied thereto; skew data storage means for set pulse and for reset pulse, said skew data storage means storing therein skew adjusting delay data for a propagation path of a delay data for set pulse and for a propagation path of a delay data for reset pulse, respectively; operation means for set pulse and for reset pulse, said operation means performing an operation of the set pulse delay data, the skew adjusting delay data for set pulse and a fraction data in each test cycle externally supplied thereto and an operation of the reset pulse delay data, the skew adjusting delay data for reset pulse and a fraction data in each test cycle externally supplied thereto, respectively, and outputting an integer delay data and a fraction delay data for set pulse from the result of the operation and an integer delay data and a fraction delay data for reset pulse from the result of the operation, respectively; delay means for set pulse and for reset pulse, said delay means outputting at least one set pulse generating effective flag for causing a timing of a test period to delay by a delay time corresponding to the integer delay data and at least one reset pulse generating effective flag for causing a timing of a test period to delay by a delay time corresponding to the integer delay data, respectively, as well as outputting fraction delay data related to these set pulse generating effective flag and reset pulse generating effective flag, respectively; variable delay means for set pulse and for reset pulse, to which the set pulse generating effective flag and the reset pulse generating effective flag are inputted respectively, said variable delay means delaying the effective flags on the basis of the related fraction delay data, respectively; waveform outputting means outputting a waveform which is set by a set pulse supplied from said set pulse variable delay means and reset by a reset pulse supplied from said reset pulse variable delay means, for each test period; and means applying a test signal having the waveform outputted from said waveform outputting means to a semiconductor device under test.
In a preferred embodiment, the semiconductor testing apparatus further includes a delay data memory for storing therein said plurality of delay data, and said delay data selecting means comprises: a select data memory for generating data selecting information in accordance with test logical data and waveform mode information externally supplied thereto; and a multiplexer for selecting, out of the plurality of delay data supplied from said delay data memory, said at least one delay data for generating at least one set pulse and said at least one delay data for generating at least one reset pulse, by the data selecting information supplied from said select data memory.
In addition, it is preferable that said select data memory has data selecting information stored therein corresponding to waveform mode information, test logical data of current test cycle and previous test cycle, and the set pulse effective flag and the reset pulse effective flags.
The aforesaid delay data selecting means may comprise: a select data memory in which data selecting information corresponding to the waveform mode information and test logical data of current test cycle and previous test cycle is stored; and a multiplexer which is capable of selecting, out of the data selecting information inputted thereto from said select data memory and the plurality of delay data inputted thereto from a delay data memory, said at least one set pulse generating delay data and said at least one reset pulse generating delay data, and the set pulse effective flag and the reset pulse effective flag in the first half or the second half of a period signal.
The aforesaid variable delay means comprise: set pulse and reset pulse data conversion means each outputting a delay control signal corresponding to the fraction delay data; and set pulse and reset pulse variable delay circuits for delaying, on the basis of the delay control signals outputted from said data conversion means, the set pulse generating effective flag and the reset pulse generating effective flag inputted thereto, respectively.
It is preferable that the data selecting information stored in said select data memory is set such that when the test logical data is a sequence of the same logical value such as xe2x80x9c0xe2x80x9d, xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, xe2x80x9c1xe2x80x9d in adjacent test cycles, the set pulse or the reset pulse is inhibited from being consecutively inputted to said waveform outputting means.
The aforesaid set pulse delay means and the aforesaid reset pulse delay means may perform operations of the set pulse integer delay data and an output of a counter for counting a clock and of the reset pulse integer delay data and an output of a counter for counting a clock, thereby to generate set pulse and reset pulse counter data coincidence expected values, respectively, and detect coincidences between said coincidence expected values and the output of said counter and output the set pulse generating effective flag and the reset pulse generating effective flag as well as the set pulse fraction delay data and the reset pulse fraction delay data related to these effective flags, respectively.